1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the handling of unhandled operations within systems supporting multiple instruction sets.
2. Description of the Prior Art
It is known to provide data processing systems that support multiple instruction sets. An example of such systems are the Thumb enabled processors produced by ARM Limited of Cambridge, England. These Thumb enabled processors support the execution of both 32-bit ARM instructions and 16-bit Thumb instructions.
Within a data processing system it can sometimes occur that a program instruction cannot be handled directly by the data processing system. Accordingly, it is known to provide mechanisms that handle such unhandled operations. An example of such a situation is prefetch instruction aborts. It is known that when prefetching instructions in a virtual memory system an instruction load can cross a page boundary and an abort can occur due to the new page not yet being properly mapped within the virtual memory system. The correct mapping can then be put in place and the instruction prefetch reissued.
A further example of such a situation is the execution floating point instructions. It is known that during execution of a floating point operation situations may occur which cannot be handled directly by the data processing system. This is particularly true of floating point systems compatible with the IEEE 754 specification. Examples of such situations are division by zero, any operations involving a NaN, any operation involving an infinity or certain operations involving denormalised numbers.
A problem arises in that when a new instruction set is added considerable effort and development is needed to ensure that appropriate abort mechanisms for all the aborts that can occur are in place.
A particular problem arises when an unhandled floating point operation occurs. Many systems rely on examination of the instruction stream to determine the floating point operation that was not handled. With a new instruction set these systems have to be rewritten to cater for the new instruction set. In addition a problem occurs when the new instruction set can generate multiple floating point operations for a single instruction of the new instruction set. In this case it may be impossible to the system to determine which floating point operation was not handled by examination of the instruction stream since a single instruction may give rise to more than one unhandled floating point operation.
A further problem occurs when the unhandled floating point operations are imprecise, that is to say, the unhandled floating point operation is not detected at the point at which the instruction generating the floating point operation is executed, but instead is detected some time later. This situation occurs because of the parallel nature of many floating point systems. The data processing system on encountering an instruction specifying a floating point operation issues the floating point operation to a floating point subsystem. Once the floating point operation has been issued to the floating point subsystem, the main data processing system continues execution of further instructions in the instruction stream. Many instructions may be executed before the floating point subsystem detects the unhandled floating point operation and signals the unhandled operation condition to the main data processing system. In this case the cause of the unhandled floating point operation cannot be determined by examination of the instruction stream. It is known in cases like this for the floating point system to contain a register which identifies the unhandled floating point operation, for example the Vector Floating Point system produced by ARM Limited of Cambridge, England.
In many systems it is not possible for the floating point subsystem to signal an unhandled operation to the main data processing system at an arbitrary point, unhandled operations may only be signalled to the main data processing system at well defined points where the main data processing system performs a handshake with the floating point subsystem. Typically these handshakes only occur on execution of an instruction specifying a floating point operation. In this case an unhandled floating point operation cannot be signalled to the main data processing system until the main data processing system executes a further instruction specifying a floating point operation.
The introduction of a new instruction set which may perform multiple floating point operations per instruction in conjunction with imprecise unhandled floating point operations causes very difficult problems or makes it impossible for the system to handle the unhandled floating point operation. The system cannot determine which instruction caused the unhandled floating point operation and it further cannot determine where execution in the instruction stream should continue once the unhandled floating point operation has been handled.